BM13xx ASIC Chip Notes
BM1380 55 nm Tested
The Bitmain Antminer BM1380 chip has only 2 readable registers:
0x0004 (used to set the clock speed) and 0x0008
(a counter for the number of nonces consumed). Attempting to read any
other register returns 0x13809000 — the 1380
portion likely relates to the chip name; the 9000 suffix is
currently unexplained. During testing I address the registers as 0x00--, but
considering that there is only a 8 bit decoder from now on I will refer to them as 0x08
and 0x04.
| Opcode | Function |
|---|---|
0x82 | Writes the operating frequency to the 0x04 register |
0x83 | Responds (self-test) |
0x84 | Responds (read register) |
0x03 | Alias of 0x83 |
0x04 | Alias of 0x84 |
0x05 | Should deactivate all but one of the chips on the chain |
0x05
and should have a register 0x00 storing its address, but I have not yet been able to find this register
nor verify that 0x05 works. However, after looking at the datasheet, for the BM1380 I think that the address
is electronically wired rather then defined.
BM1381
Bitmain does not appear to have produced this chip, or at least no evidence of its existence has surfaced.
BM1382 28 nmUntested
Very similar to the BM1380. The prevailing theory is that the architecture
was revised mid-production, making the BM1382 essentially a die-shrink
successor to the BM1380 — the same design on a smaller 28 nm
process node compared to the BM1380's 55 nm. There is a
degree of cross-compatibility as a result.
BM1383
Bitmain does not appear to have produced this chip, or at least no evidence of its existence has surfaced.
BM1384 28 nmUntested
The BM1384 exposes a much wider opcode surface than the BM1380. It operates at 6.25–500 MHz - similiar to that of the BM1380 - and contains 55 SHA-256 cores (implying the BM1380 has approximately 11–12 cores if the SHA-256 architecture is comparable).
| Opcode | Function |
|---|---|
0x01 | Set chip address |
0x82 | Set chip frequency (same role as BM1380) |
0x83/0x03 | Undocumented — possibly the same self-test as BM1380; 0x08 nonce counter register presumably present |
0x84/0x04 | Read from register (same as BM1380) |
0x85/0x05 | Stop all chips on the chain |
0x86 | GATEBLK — purpose not yet determined |
BM1385 28 nmUntested
The BM1385 is similar to the BM1384 in terms of opcode support, but it may use a significantly different — or at least improved — architecture. It delivers roughly 50% more hashrate while using about 50% less power. I personally think the architectural change was likely modest, especially since Bitmain published a related patent just a month earlier. You can view it here: CN105245327A Patent . The patent essentially describes rehashing only the data that actually needs to be rehashed, while skipping anything that doesn’t; an optimization that could easily account for most of the performance gains.
| Opcode | Function |
|---|---|
0x01 | Set chip address |
0x83 | Undocumented — possibly the same self-test as BM1380; 0x08 nonce counter register presumably present |
0x84/0x04 | Read from register (same as BM1380) |
0x85/0x05 | Stop all chips on the chain |
0x88/0x08 | Writes a configuration register on a target chip |
BM1386
Bitmain does not appear to have produced this chip, or at least no evidence of its existence has surfaced.
BM138716 nmUntested
The BM1387 supports ASIC-Boost, accompanied by a significant architectural revision. The opcode scheme is completely different from earlier chips in the BM13xx line.
| Opcode | Function |
|---|---|
0x54 | Probe — instructs chips to identify themselves; used to count chips on the chain |
0x58 | Broadcast settings (frequency, gate block, etc.) to all chips |
0x48 | Write settings to a single chip (single-chip variant of 0x58) |
0x55 | Deactivate all chips |
0x41 | Deactivate a single chip |
0x40 | Deactivate a family of chips |
0x21 | Send work to chips |